1. Technical Field of the Invention
The present invention relates to a semiconductor device and a method for forming the same and, more particularly, to a gate-contact structure and a method for forming the same.
2. Description of Related Art
As an integration level of semiconductor devices increases, a structure in which there is no space between a contact plug and a device isolation layer pattern, normally called “a borderless contact structure”, is being widely used. The method for forming the semiconductor device including the borderless contact structure comprises forming an etch stop layer on the device isolation layer pattern. Thus, when patterning an interlayer insulation layer for forming a contact hole, the device isolation layer pattern is not etched.
Meanwhile, the conventional method for forming a gate electrode of the semiconductor device comprises patterning a gate conductive layer formed on a semiconductor substrate using a photoresist pattern. However, as semiconductor devices gradually become highly integrated, it grows increasingly difficult to minutely form a width of the gate electrode, especially when the gate electrode of a flash memory device has a structure in which various kinds of material layers are sequentially stacked. To solve the foregoing problem, a method for forming the flash memory device includes forming a capping pattern on the gate conductive layer, then etching the gate conductive layer using the capping pattern as an etch mask.
FIGS. 1 and 2 are top plan views illustrating a method of forming a gate-contact structure for a NOR-type nonvolatile memory device according to a conventional method. FIGS. 3A through 3C and 4A through 4C are cross-sectional views illustrating a method for forming the gate-contact structure of the NOR-type nonvolatile memory device according to the conventional method. FIGS. 3A through 3C are the cross-sectional views taken along lines 1–1′, 2–2′, and 3–3′ of FIG. 1, respectively, and FIGS. 4A through 4C are the cross-sectional views taken along lines 1–1′, 2–2′, and 3–3′ of FIG. 2, respectively.
Referring to FIGS. 1 and 3A through 3C, a plurality of device isolation layer patterns 12 are formed at a semiconductor substrate 10 to define an active region 70. A gate oxide layer 14 is formed on the active region 70. A gate conductive layer (not shown) and a capping pattern 28 are sequentially stacked on the semiconductor substrate including the gate oxide layer 14. In this case, the capping pattern 28 is formed to cross the active region 70 as well as the device isolation layer pattern 12. By using the capping pattern 28 as an etch mask, the gate conductive layer is patterned to form a gate electrode 20. Thus, the gate electrode 20 and the capping pattern 28, which are sequentially stacked, constitute a gate pattern 30. In case of a cell transistor used for the flash memory device, the gate electrode 20 is preferably formed of polysilicon, a gate interlayer insulation layer, polysilicon, and silicide, which are sequentially stacked.
A photoresist layer is formed on an entire surface of the semiconductor substrate including the gate pattern 30. The photoresist layer is patterned to form a photoresist pattern 40, which has an opening 42 exposing the device isolation layer pattern 12 disposed at one side of the gate pattern 30. The photoresist pattern 40 covers the device isolation layer pattern 12 at the other side of the gate pattern 30 where the opening 42 is not formed. By using the photoresist pattern 40 as an etch mask, the exposed device isolation layer pattern 12 is removed to expose the semiconductor substrate 10.
Referring to FIGS. 2 and 4A through 4C, after removing the photoresist pattern 40, an ion implantation process is performed by using the gate pattern 30 as an ion implantation mask, thereby forming a common source junction region 82 and a drain junction region 80 in the semiconductor substrate 10. At this time, another photoresist pattern may be used as the ion implantation mask together with the gate pattern 30. The common source junction region 82 is formed in the semiconductor substrate 10 exposed by removing the active region 70 as well as the device isolation layer pattern 12. The drain junction region 80 is formed in the active region 70 covered with the photoresist pattern 40.
An etch stop layer 50 and an interlayer insulation layer 60 are sequentially stacked on an entire surface of the semiconductor substrate including the junction regions 80 and 82. The interlayer insulation layer 60 and the etch stop layer 50 are patterned to form a gate contact hole 64 and a junction region contact hole 62. The gate contact hole 64 and the junction region contact hole 62 expose top surfaces of the gate pattern 30 and the drain junction region 80, respectively.
As described above, the etch stop layer 50 is a material layer that is required for forming the borderless contact structure. That is, the etch stop layer 50 is used to prevent the device isolation layer pattern 12 from being etched during etching of the interlayer insulation layer 60. At this time, the capping pattern 28 of a lower part of the gate contact hole 64 still covers the gate electrode 20. Thus, it is necessary to perform an additional process for etching the capping pattern 28 so as to form a capping contact hole 66 exposing a top surface of the gate electrode 20. Otherwise, the semiconductor device may suffer a serious problem because it is difficult to apply an operating voltage to the gate electrode 20.
However, in case the additional etch process is performed, since the etch stop layer 50 was etched in the junction region contact hole 62, the drain junction region 80 is recessed. Besides, in case the semiconductor device has the borderless contact structure as described above, the additional etch process of the silicon oxide layer leads to etching of the device isolation layer pattern 112 exposed through the junction region contact hole 62. As a result, there arises a dent 99, as illustrated by the dotted circle. The dent 99 may cause a leakage current to flow through the drain junction region 80. To prevent the dent 99, the gate contact hole 64 and the junction region contact hole 62 may be separately formed. This is undesirable from both a process simplification and reduction of fabrication costs perspective.